The present invention relates generally to the propagation of electrical signals over electrical conducting wires, and, more particularly to the propagation of electrical signals on wires on integrated circuits.
The wires that propagate signals between logic stages on an integrated circuit can be implemented in different widths. The chosen width for such wires in a given integrated chip has significant affects on the propagation characteristics of the signal being carried over the wires. For example, relatively wide wires physically consume more space and have relatively lower levels of resistance. The lower resistance level results in relatively faster signal transition times on the wire, thereby generating faster signal propagation through the integrated circuit. But the lower resistance also amplifies the inductive characteristics of the wire, which generally causes the peaks of the propagating signal to be undershot or overshot, thereby causing “ringing” on the line and thus reducing the signal integrity and reliability. On the other hand, relatively narrow wires consume less space on the integrated circuit and have relatively higher levels of resistance. The higher resistance level on the wires decreases the inductive characteristics of the wire, but amplifies the capacitive characteristics of the wire. As a result, the quality (transition slope) and propagation speed of the signal over the wire is degraded. Designers of integrated circuits must consider these types of effects associated with the width of the wires when designing integrated circuit applications. Oftentimes, designers of integrated circuits balance the positive and negative effects of different wire sizes to arrive at an optimal wire size for a given application.
Certain integrated circuit applications, such as clock nets, require very fast signal transition times on the wires. To achieve the required signal transition times, such applications commonly use relatively wide wires to propagate signals between logic stages. As described above, the use of relatively wide wires results in ringing on the wire caused by the increased inductive characteristics caused by the relatively lower resistance. To reduce the undesirable affects associated with the increased inductive characteristics of the relatively wide wires, it is typical to incorporate “shields” for the wires on the integrated circuits. The “shields” comprise electrical conducting strips or wires positioned parallel to and on both sides of the signaling wire. FIG. 1 illustrates an exemplary signaling wire 12 having two shields 14a and 14b on either side of the signaling wire 12 on an integrated circuit. Both shield wires 14a and 14b are connected to a ground grid. This application of shielding a signaling wire with grounded shielding wires is referred to herein as “passive shielding.” Still referring to FIG. 1, an input signal (sometimes referred to herein as the “signal of interest”) is boosted by an inverter gate 16 (as is common) before being applied to the signaling wire 12. At the end of the signaling wire 12, the signal is inverted again (by inverter 18) to return the signal to its original polarity as an output signal. As the input signal propagates down the signaling wire 12, the shield wires 14a and 14b reduce the inductive effects of the signaling wire 12 and the associated overshoot/undershoot and ringing effects.
While passive shielding of signaling wires on an integrated chip improves the signal propagation characteristics of the signaling wires, it does not improve the characteristics enough for certain very wide wires, such as clock nets on integrated circuits. For very wide wire applications, it is common to split the signaling wire up into multiple “fingers”, wherein the collective widths of the “fingers” equals the width of the original signaling wire (had it not been split up). The signal propagates down the “fingers” and is combined at the end of the wire. FIG. 2 illustrates a signaling wire split into two fingers 12a and 12b, each of which being connected to the input signal CLK through inverter 16. The fingers 12a and 12b are shielded by shielding wires 14a and 14b on the outer sides and by shielding wire 14c between the fingers 12a and 12b. By splitting the signaling wire into multiple fingers 12a and 12b, the adverse affects associated with the inductance of the signaling wire are reduced, but the increased resistive nature (of the wires 12a and 12b) results in a degradation of the signal switching quality and signal propagation speed associated with the signaling wires.
Therefore, the inventors hereof have recognized the need for a system and method that reduces the adverse affects associated with inductive signaling wires on integrated circuits (such as overshoot/undershoot and ringing affects) while maintaining or improving desirable signal propagation characteristics (such as fast signal transitions and propagation speeds).